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Allowing Computing Errors Could Help Boost Chip Efficiency, Power

Allowing Computing Errors Could Help Boost Chip Efficiency, Power

Photo: Un ragazzo chiamato Bi/Flickr (CC)

Levi Beckerson

May 26, 2010

Modern computer processor engineers face a myriad of problems as they scrabble to create more powerful chips. This is especially true of Intel and AMD, who together produce nearly all of the processors used in consumer grade desktops, laptops, tablets, and netbooks.

Two of the most immediate problems are transistor size and heat dissipation as a byproduct of increased power requirements to keep them running correctly. As transistors shrink and are packed ever more closely together, they require more power to keep working flawlessly. These modern microchips are made to produce no errors and this, University of Illinois assistant professor of computer engineering Rakesh Kumar says, is holding them back from being more power efficient, more powerful, and more cost-effective.

Rather than continuing to push the physical limits of processors, Kumar believes a shift to a new type of computing, which embraces random processing errors caused by “defective” chips could especially help to combat the relatively massive power needs in state-of-the-art processors. He outlines these “stochastic processors” in an interview with the BBC.

This new approach would heavily involve software designed to deal with often inconsequential but occasionally system-crashing processing errors. However, the reduced power consumption from the system could result in as much as a 30% drop in requirements. This would further translate into less heat generated — something that would be especially welcome in mobile electronics.

Kumar’s idea would require a paradigm shift in software programming. Though most applications are equipped to deal with expected errors, the unexpected often cause the application to terminate and even whole-system crashes. The new software could have many functions, including dealing with simple errors by telling the CPU to take its time with the instruction or comparing an error to past errors in order to determine how to handle the unexpected.

Though this method of processor utilization would obviously not be compatible with current computers, it may be simple enough to implement in the future. Consumers, who are largely oblivious to the inner workings of their computers, won’t be the hard sell here.

Intel, AMD, IBM, VIA and other processor manufacturers, on the other hand, could require a little convincing.

_© 2009, DailyTech.

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